Daily Image
23-07-2015
Breaking the 1Tbps barrier with UniBoard2
| Submitter: | Leon Hiemstra, Jonathan Hargreaves and Gijs Schoonderbeek |
| Description: | Engineering is about pushing the envelope. With UniBoard2 we wanted to break the Tbps barrier(*), and that is exactly what we have done. During a visit by Peter Schepers from Altera Inc. and Karl de Boois from EBV, the nitty-gritty details of their transceivers where explained to us. Within a week after that, we breached the 1Tbps barrier. This was done(**) by using twenty-four 10Gbps transceivers on the backplane side of the board for each FPGA (making in total 960 Gbps full duplex), and twenty-four optical interconnections on the front side per node (making in total 960Gbps). Although we were the first to use the Arria10 FPGAs from Altera, we were able to achieve error rates smaller than 1E-13 (one error per 10 Tbits). Last week, we were able to run all 96 transceivers for a single node (almost 1Tbps per node). This will be the target for all FPGAs on the production boards by the end of the year. From left to right, the victorious team consists of: Leon Hiemstra (firmware engineer Astron), Karl de Boois (Field Application Engineer EBV), Gijs Schoonderbeek (hardware design Astron), Peter Schepers (transceiver specialist Altera) and Jonathan Hargreaves (firmware engineer JIVE). (*) One Terabit per second (Tbps) is 1.000.000.000.000 bps, or 100.000 HDX 1080p video streams. The aggregated traffic on all AMS-IX (Amsterdam Internet Exchange) connected network ports has a peak of 3.7 Tbps, which can be handled by a single UniBoard2 when all 384 transceivers are used. (**) We do not apologize about the jargon. It just says it all. |
| Copyright: | DESP |
| Tweet |  |